(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to an improved process for the formation of polycide used for the gate electrode or interconnect metallization in integrated circuit devices.
(2) Description of Related Art
In the manufacture of semiconductor devices, the formation of conductive lines, such as the gate electrode in a MOSFET device or interconnections between IC devices, is a critical step in producing functioning and reliable circuits. Polycrystalline silicon is a material which is commonly used to form such gate electrodes and interconnections. In order to increase the conductivity of these gate electrodes and interconnection lines, a refractory silicide, such as tantalum silicide, is deposited on top of the polysilicon. Such a structure is referred to as polycide.
Numerous improvements to the polycide deposition process have been invented. For example, U.S. Pat. No. 5,510,296 entitled "Manufacturable Process For Tungsten Polycide Contacts Using Amorphous Silicon" granted Apr. 23, 1996 to Haw Yen et al describes a method of tungsten polycide formation in which amorphous silicon is deposited by LPCVD processing, followed by deposition of tungsten silicide by LPCVD processing using SiH.sub.4 and WF.sub.6, and annealing the structure in nitrogen at a temperature between about 750.degree. and 850.degree. C. for a time between about 30 and 60 minutes.
Also, U.S. Pat. No. 5,459,087 entitled "Method of Fabricating a Multi-layer Gate Electrode With Annealing Step" granted Oct. 17, 1995 to Akira Mochizuki describes a method of forming a gate electrode including a tungsten silicide layer. The method performs a nitrogen anneal of a tungsten layer prior to sputtering a tungsten silicide layer.
U.S. Pat. No. 5,364,803 entitled "Method of Preventing Fluorine-Induced Gate Oxide Degradation in Wsi.sub.x Polycide Structure" granted Nov. 15, 1994 to Water Lur et al describes a method of tungsten polycide formation in which polysilicon is deposited, followed by deposition of a thin diffusion barrier layer consisting of tantalum nitride, then depositing tungsten silicide, and annealing the structure in nitrogen and oxygen at a temperature between about 800 and 1050.degree. C. for a time between about 10 and 60 minutes.
U.S. Pat. No. 5,306,951 entitled "Sidewall Silicidation For Improved Reliability and Conductivity" granted Apr. 26, 1994 to Roger R. Lee et al describes a structure for formation of a refractory silicide by depositing the refractory metal by sputtering on the sidewalls as well as the top of a polysilicon structure, thereby resulting in a more conductive structure.
While these inventions result in improvements to the polycide deposition process they do not address critical IC device manufacturability issues, such as interaction of previous and subsequent processing steps, overall process yield, device reliability, and cost.
The present invention is directed to a novel and improved process for the formation of polycide used for the gate electrode or interconnect metallization in integrated circuit devices, wherein manufacturability, manufacture process yield, and device reliability are improved.